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for a rewarding career in cutting edge semiconductor product &
ip design development. you can mail your resume to joinus@mandatecc.com in case your skill sets match any of the below job opening.
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position |
sr design engineer |
job location |
bangalore |
qualification |
b e / b
tech / m tech / m s / m sc / m e(electronics &
communication / vlsi / electronic & electrical) |
experience |
4 - 8 years |
skills |
- drc, lvs
- cmos design
- cadence virtuoso, encounter, mentor calibre, synopsys,
circuit simulation & static timing tools
- place n route
- cdr, pll. adc, dac, serdes, knowledge of jitter analysis,
characterization and modeling, floorplan and layout guidelines, tx, rx
- system level timing budget, signal integrity, and power
integrity
- cadence custom design tools
- hands on experience on chip design eda tools
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job responsibilities |
- lead design and implementation of
high speed interface circuit
- design projects include high
speed transceivers and high frequency plls
- design, simulation and verification
of analog & mixed-signal circuits
- provide floorplan and layout guidelines
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solve challenges of circuit design in deep submicron cmos
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extensive design experience in tx, rx, cdr, pll for high speed io
interfaces
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fully proficient in understanding of industry communication
standards and test equipment tools
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generate design review documentation.
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interface with other design team members and provide directions to
layout and other design engineers, ensuring that electrical
performance meets specifications and requirements
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candidate profile |
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in-depth understanding of deep submicron cmos
process and related circuit design issues.
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experience in silicon bring-up & debugging
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knowledge in system level timing budget, signal
integrity, and power integrity.
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working knowledge of cadence custom design tools
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participate and be a key contributor in block &
chip level architectures.
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assist in architecture, layout, integration,
bring-up, post silicon debugging, and
characterization
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position |
sr design engineer |
job location |
bangalore |
qualification |
b e / b
tech / m tech / m s / m sc / m e (electronics &
communication / vlsi / electronic & electrical) |
experience |
4 - 8 years |
skills |
- ic circuit design
- scripting languages like perl & skill
- hands on experience on chip design eda tools
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job responsibilities |
- defining specifications at the
block level, designing and simulations of analog
blocks
- close supervision of layout
and floor planning
- documentation of analog
circuit blocks
- active participation in
prototype evaluation
- implementation tool &
methodology, working experience on scripting
languages like skill, perl
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candidate profile |
- analog ic circuit design,
simulation and verification.
- good understanding of cmos and
bipolar transistor design preferably has
experience in bcdmos process.
- design of analog blocks like
power amplifier, instrumentation
amplifier,inductive load h-bridge drivers, low
power opamps, offset cancellation comparators,
bandgap and regulators.
- design of linear and switching
motor drivers for dc brushless, dc brush, stepper
motor
- good understanding of
different test equipments. bench evaluation of ic
performance as well as system performance in
intended application.
- the candidate should be highly
motivated who possess strong communication skills
with good strategic thinking capabilities and
adaptable to work in a dynamic environment with
various functional and global teams.
- knowledge of chip design flow
for analog and mixed signal chips and working
knowledge of chip test and debug capabilities
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|
| |
position |
sr design engineer |
job location |
bangalore |
qualification |
b e / b
tech / m tech / m s / m sc / m e(electronics &
communication / vlsi / electronic & electrical) |
experience |
4 - 8 years |
skills |
- serdes, cad tools / flow
- drc, lvs
- cmos design
- cadence virtuoso, encounter, mentor calibre, synopsys
circuit simulation & static timing tools
- place n route
- hands on experience on chip design eda tools
|
job responsibilities |
- lead design and implementation of
high speed interface circuit
- design projects include high speed
transceivers and high frequency plls
- design, simulation and verification
of analog & mixed-signal circuits
- provide floorplan and layout
guidelines
- solve challenges of circuit design
in deep submicron cmos
- extensive design experience in tx,
rx, cdr, pll for high speed io interfaces
- participate and be a key contributor
in block & chip level architectures.
- assist in architecture, layout,
integration, bring-up, post silicon debugging, and
characterization.
- generate design review
documentation.
- interface with other design
team members and provide directions to layout and
other design engineers, ensuring that electrical
performance meets specifications and requirements.
- fully proficient in
understanding of industry communication standards
and test equipment tools
|
candidate profile |
- in-depth understanding of deep
submicron cmos process and related circuit design
issues.
- experience in silicon bring-up
& debugging
- knowledge in system level
timing budget, signal integrity, and power
integrity.
- working knowledge of cadence
custom design tools
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| |
position |
sr design engineer |
job location |
bangalore |
qualification |
b e / b tech / m tech / m s / m sc / m
e (electronics & communication / vlsi / electronic &
electrical) |
experience |
4 - 8 years |
job responsibilities |
- process design kit (pdk) development group focuses on using
the technology design rules to develop, test and deploy design kits, for use in
designing analog and digital ics using the cadence ic design tools.
- improve design efficiency and productivity of design teams,
and reduce design cycle time.
- pdk development including verification rules writing (erc.
emi and ir drop).
- responsible for developing, testing and releasing erc and
emi rules, flow and documentation, ir drop analysis flow and documentation and
power analysis flow and documentation for all of our internal and external
technologies, using the cadence tools. development covers analog, digital and
mixed signal technologies.
- must be able to understand the design rule document,
translate and program rules into an accurate, usable and flexible pdk for use
with the cadence ic mixed signal design tools.
- must have a good knowledge of the asusra tools and skill
language programming.
- work with the design teams, device design and device
characterization groups to understand specifications and requirements.
- must have strong teamwork, communication skills and work
ethics with the ability to address changes and issues with the device design and
device characterization groups in a consistent and effective way.
- respond effectively to design center requests in a timely
and consistent manner.
- write pdk user documentation while meeting ir’s document
control quality standard.
- apply formal configuration & release management methods,
project planning, and software qa methods.
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candidate profile |
- prior experience in pdk
development
- familiar with the ic design
process, front-to-back
- experience with the cadence ic
design tools, especially vavo/eps, qrc and assura
lvs/rcx
- strong programming capability
using skill, perl and shell scripting languages
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strong
back end verification experience
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skills
in the practice of formal software development
methodologies, including but not limited to:
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bsee/msee
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good
understanding of erc, emi rules and impact on
final chip verification and cycle time reduction
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thorough familiarity with the cadence design tools
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ability
to work in a team environment and participate in
cross-functional activities
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